1. Field of the Invention
The invention relates generally to logic synthesis, and more particularly, to the synthesis of combinational circuits with cycles.
2. Description of the Related Art
Increased complexity in digital logic circuits make the use of logic synthesis essential for all but the simplest designs. Conventional logic circuits are made up of combinational and sequential circuits. A type of logic circuit, referred to as a combinational circuit, has outputs that depend only on the current values of the circuit's inputs. Because their outputs depend only on the current values of their inputs, combinational circuits are referred to as being “memoryless”. Another type of logic circuit, referred to as a sequential circuit, has outputs that may depend upon past as well as current values of the circuit's inputs, in other words a sequential circuits has “memory”. Combinational circuits are generally thought of as acyclic, that is as feed-forward or loop-free, structures while sequential circuits are thought of as cyclic structures that include loops. In fact, “combinational” and “sequential” are often defined in this way.
In a conventional logic synthesis system, a front-end process accepts a high level description of the design, such as a hardware description language (HDL) design that typically specifies input variables, internal variables, and output variables, and converts the high level description into a set of boolean equations that describe the system. The logic synthesis system, or tool, then optimizes a multilevel network description of the design that generally includes both combinational and sequential circuits. The optimization procedures generally are applied to produce smaller, faster representations of the design. A back-end process produces a final circuit design based on the technology of the target device in which the design will be implemented.
As designs become larger and more complex, synthesis tools need to design circuits that are optimized according to a number of possible criteria. Minimization of the area that a circuit occupies on a target device allows for more complex designs to be implemented on a device of a given size. Also, reducing the area required to implement an existing design may allow it to be implemented on a smaller target device. Minimizing the delay of a circuit allows for a higher clock speed, resulting in a faster, more efficient circuit. Other optimization criteria can include reducing power consumption, increased fault tolerance, and increased testability.
Therefore, there is a need for an improved method and apparatus for synthesis of circuits.